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path: root/target/arm/translate-mve.c
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* target/arm: Implement MVE VADDLVPeter Maydell2021-07-021-0/+63
* target/arm: Implement MVE VSHLCPeter Maydell2021-07-021-0/+30
* target/arm: Implement MVE saturating narrowing shiftsPeter Maydell2021-07-021-0/+12
* target/arm: Implement MVE VSHRN, VRSHRNPeter Maydell2021-07-021-0/+15
* target/arm: Implement MVE VSRI, VSLIPeter Maydell2021-07-021-0/+3
* target/arm: Implement MVE VSHLLPeter Maydell2021-07-021-0/+15
* target/arm: Implement MVE vector shift right by immediate insnsPeter Maydell2021-07-021-0/+5
* target/arm: Implement MVE vector shift left by immediate insnsPeter Maydell2021-07-021-0/+51
* target/arm: Implement MVE logical immediate insnsPeter Maydell2021-07-021-0/+50
* target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculationPeter Maydell2021-07-021-8/+9
* target/arm: Make VMOV scalar <-> gpreg beatwise for MVEPeter Maydell2021-06-241-2/+2
* target/arm: Implement MVE VADDVPeter Maydell2021-06-241-0/+43
* target/arm: Implement MVE VHCADDPeter Maydell2021-06-241-1/+3
* target/arm: Implement MVE VCADDPeter Maydell2021-06-241-0/+7
* target/arm: Implement MVE VADC, VSBCPeter Maydell2021-06-241-0/+37
* target/arm: Implement MVE VRHADDPeter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VQDMULL (vector)Peter Maydell2021-06-241-0/+30
* target/arm: Implement MVE VQDMLSDH and VQRDMLSDHPeter Maydell2021-06-241-0/+4
* target/arm: Implement MVE VQDMLADH and VQRDMLADHPeter Maydell2021-06-241-0/+4
* target/arm: Implement MVE VRSHLPeter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VSHL insnPeter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VQRSHLPeter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VQSHL (vector)Peter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VQADD, VQSUB (vector)Peter Maydell2021-06-241-0/+4
* target/arm: Implement MVE VQDMULH, VQRDMULH (vector)Peter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VQDMULL scalarPeter Maydell2021-06-241-0/+30
* target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)Peter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VQADD and VQSUBPeter Maydell2021-06-241-0/+4
* target/arm: Implement MVE VPSTPeter Maydell2021-06-241-0/+59
* target/arm: Implement MVE VBRSRPeter Maydell2021-06-241-0/+1
* target/arm: Implement MVE VHADD, VHSUB (scalar)Peter Maydell2021-06-241-0/+4
* target/arm: Implement MVE VSUB, VMUL (scalar)Peter Maydell2021-06-241-0/+2
* target/arm: Implement MVE VADD (scalar)Peter Maydell2021-06-241-0/+45
* target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVHPeter Maydell2021-06-211-0/+24
* target/arm: Implement MVE VMLSLDAVPeter Maydell2021-06-211-0/+11
* target/arm: Implement MVE VMLALDAVPeter Maydell2021-06-211-0/+96
* target/arm: Implement MVE VMULLPeter Maydell2021-06-211-0/+4
* target/arm: Implement MVE VHADD, VHSUBPeter Maydell2021-06-211-0/+4
* target/arm: Implement MVE VABDPeter Maydell2021-06-211-0/+2
* target/arm: Implement MVE VMAX, VMINPeter Maydell2021-06-211-0/+4
* target/arm: Implement MVE VRMULHPeter Maydell2021-06-211-0/+2
* target/arm: Implement MVE VMULHPeter Maydell2021-06-211-0/+2
* target/arm: Implement MVE VADD, VSUB, VMULPeter Maydell2021-06-211-0/+16
* target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEORPeter Maydell2021-06-211-0/+37
* target/arm: Implement MVE VDUPPeter Maydell2021-06-211-0/+27
* target/arm: Implement MVE VNEGPeter Maydell2021-06-211-0/+15
* target/arm: Implement MVE VABSPeter Maydell2021-06-211-0/+15
* target/arm: Implement MVE VMVN (register)Peter Maydell2021-06-211-0/+5
* target/arm: Implement MVE VREV16, VREV32, VREV64Peter Maydell2021-06-211-0/+33
* target/arm: Implement MVE VCLSPeter Maydell2021-06-211-0/+1