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path: root/target/riscv/cpu_bits.h
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* target/riscv: Add *envcfg* CSRs supportAtish Patra2022-04-221-0/+39
* target/riscv: Add support for mconfigptrAtish Patra2022-04-221-0/+1
* target/riscv: add support for svpbmt extensionWeiwei Li2022-02-161-0/+2
* target/riscv: add support for svnapot extensionWeiwei Li2022-02-161-0/+1
* target/riscv: Ignore reserved bits in PTE for RV64Guo Ren2022-02-161-0/+3
* target/riscv: Add defines for AIA CSRsAnup Patel2022-02-161-0/+119
* target/riscv: Implement hgeie and hgeip CSRsAnup Patel2022-02-161-0/+1
* target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel2022-02-161-0/+3
* target/riscv: Enable uxl field writeLIU Zhiwei2022-01-211-0/+3
* target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot2022-01-081-0/+3
* target/riscv: rvv-1.0: add vlenb registerGreentime Hu2021-12-201-0/+1
* target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei2021-12-201-0/+7
* target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei2021-12-201-0/+1
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-201-0/+1
* target/riscv: remove force HS exceptionJose Martins2021-10-291-6/+0Star
* target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo2021-10-281-0/+96
* target/riscv: Create RISCVMXL enumerationRichard Henderson2021-10-211-3/+5
* target/riscv: Remove some unused macrosAlistair Francis2021-10-211-8/+0Star
* target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-211-4/+4
* target/riscv: Update the ePMP CSR addressAlistair Francis2021-09-201-2/+2
* target/riscv: fix wfi exception behaviorJose Martins2021-06-081-0/+1
* target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-111-11/+0Star
* target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-111-10/+0Star
* target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-111-11/+0Star
* target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Define ePMP mseccfgHou Weiying2021-05-111-0/+3
* target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-111-21/+23
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-23/+0Star
* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+1
* riscv: Add semihosting supportKeith Packard2021-01-181-0/+1
* target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-181-3/+1Star
* target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson2020-12-181-2/+2
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-101-1/+0Star
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-15/+4Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-0/+6
* target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2020-08-251-0/+3
* target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis2020-08-251-6/+8
* target/riscv: Update the Hypervisor trap return/entryAlistair Francis2020-08-251-0/+1
* target/riscv: Convert MSTATUS MTL to GVAAlistair Francis2020-08-251-2/+3
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+1
* target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis2020-08-251-0/+1
* target/riscv: support vector extension csrLIU Zhiwei2020-07-021-0/+15
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-271-0/+11
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+3
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-271-0/+7
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-271-0/+6
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-271-0/+3
* target/riscv: Rename the H irqs to VS irqsAlistair Francis2020-02-271-6/+6
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-271-16/+19
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