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* cpu-timers, icount: new modulesClaudio Fontana2020-10-051-2/+2
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-231-1/+1
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson2020-09-181-0/+1
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-134-12/+27
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| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-103-5/+9
| * target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-5/+2Star
| * target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2020-09-102-0/+2
| * target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-103-2/+14
* | Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell2020-09-111-10/+7Star
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| * | Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
| * | Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
| * | Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
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* / trace-events: Fix attribution of trace points to sourceMarkus Armbruster2020-09-091-1/+1
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* softfloat: Implement the full set of comparisons for float16Kito Cheng2020-08-281-25/+0Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-255-6/+109
* target/riscv: Return the exception from invalid CSR accessesAlistair Francis2020-08-252-29/+35
* target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2020-08-252-0/+43
* target/riscv: Only support little endian guestsAlistair Francis2020-08-251-0/+5
* target/riscv: Only support a single VSXL lengthAlistair Francis2020-08-251-0/+9
* target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis2020-08-251-6/+8
* target/riscv: Update the Hypervisor trap return/entryAlistair Francis2020-08-254-26/+9Star
* target/riscv: Fix the interrupt cause codeAlistair Francis2020-08-251-2/+3
* target/riscv: Convert MSTATUS MTL to GVAAlistair Francis2020-08-253-9/+26
* target/riscv: Don't allow guest to write to htinstAlistair Francis2020-08-251-1/+0Star
* target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-35/+25Star
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-256-0/+474
* target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis2020-08-253-0/+21
* target/riscv: Change the TLB page size depends on PMP entries.Zong Li2020-08-223-2/+62
* target/riscv: Fix the translation of physical addressZong Li2020-08-221-2/+3
* riscv: Fix bug in setting pmpcfg CSR for RISCV64Hou Weiying2020-08-221-3/+2Star
* target/riscv: check before allocating TCG tempsLIU Zhiwei2020-08-222-8/+8
* target/riscv: Clean up fmv.w.xLIU Zhiwei2020-08-221-5/+1Star
* target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson2020-08-222-16/+73
* target/riscv: Check nanboxed inputs to fp helpersRichard Henderson2020-08-222-18/+57
* target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson2020-08-221-0/+4
* target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson2020-08-222-15/+12Star
* target/riscv: Generate nanboxed results from fp helpersRichard Henderson2020-08-222-19/+28
* meson: targetPaolo Bonzini2020-08-213-30/+36
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-2110-14/+14
* trace: switch position of headers to what Meson requiresPaolo Bonzini2020-08-211-0/+1
* target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth2020-08-051-2/+2
* target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li2020-07-221-1/+1
* target/riscv: fix vector index load/store constraintsLIU Zhiwei2020-07-221-1/+9
* target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei2020-07-221-0/+1
* target/riscv: Fix pmp NA4 implementationAlexandre Mergnat2020-07-141-1/+1
* target/riscv: fix vill bit index in vtype registerFrank Chang2020-07-141-1/+1
* target/riscv: fix return value of do_opivx_widen()Frank Chang2020-07-141-1/+1
* target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang2020-07-141-1/+1
* target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang2020-07-141-0/+5
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