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* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* target/riscv: cpu: Set XLEN independently from targetAlistair Francis2020-12-181-9/+16
* target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-182-88/+92
* target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis2020-12-181-5/+7
* target/riscv: cpu: Remove compile time XLEN checksAlistair Francis2020-12-181-9/+10
* target/riscv: Specify the XLEN for CPUsAlistair Francis2020-12-181-10/+23
* target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2020-12-182-0/+11
* target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis2020-12-182-24/+8Star
* target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis2020-12-181-0/+6
* target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson2020-12-181-2/+2
* target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang2020-12-181-1/+2
* hmp: Pass monitor to mon_get_cpu_env()Kevin Wolf2020-11-131-1/+1
* target/riscv: Split the Hypervisor execute load helpersAlistair Francis2020-11-103-42/+17Star
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-105-166/+59Star
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-104-51/+25Star
* target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis2020-11-101-13/+17
* target/riscv: Add a virtualised MMU ModeAlistair Francis2020-11-103-3/+14
* target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang2020-11-031-1/+1
* target/riscv: Add V extension state descriptionYifei Jiang2020-11-031-0/+25
* target/riscv: Add H extension state descriptionYifei Jiang2020-11-031-0/+47
* target/riscv: Add PMP state descriptionYifei Jiang2020-11-033-11/+70
* target/riscv: Add basic vmstate description of CPUYifei Jiang2020-11-034-8/+81
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-036-74/+41Star
* target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2020-10-222-12/+34
* target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer2020-10-221-3/+3
* target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer2020-10-221-1/+3
* target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer2020-10-221-1/+1
* riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2020-10-222-2/+7
* icount: rename functions to be consistent with the module nameClaudio Fontana2020-10-051-2/+2
* cpu-timers, icount: new modulesClaudio Fontana2020-10-051-2/+2
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-231-1/+1
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson2020-09-181-0/+1
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-134-12/+27
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| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-103-5/+9
| * target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-5/+2Star
| * target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2020-09-102-0/+2
| * target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-103-2/+14
* | Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell2020-09-111-10/+7Star
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| * | Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
| * | Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
| * | Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
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* / trace-events: Fix attribution of trace points to sourceMarkus Armbruster2020-09-091-1/+1
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* softfloat: Implement the full set of comparisons for float16Kito Cheng2020-08-281-25/+0Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-255-6/+109
* target/riscv: Return the exception from invalid CSR accessesAlistair Francis2020-08-252-29/+35
* target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2020-08-252-0/+43
* target/riscv: Only support little endian guestsAlistair Francis2020-08-251-0/+5
* target/riscv: Only support a single VSXL lengthAlistair Francis2020-08-251-0/+9
* target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis2020-08-251-6/+8
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