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* tcg: Add opcodes for vector minmax arithmeticRichard Henderson2019-01-281-0/+10
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add opcodes for vector saturated arithmeticRichard Henderson2019-01-281-0/+9
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: fix s/compliment/complement/ typosEmilio G. Cota2018-05-201-1/+1
| | | | | Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg: Document INDEX_mul[us]h_*Richard Henderson2018-05-011-0/+8
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add generic vector ops for multiplicationRichard Henderson2018-02-081-0/+4
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add generic vector ops for comparisonsRichard Henderson2018-02-081-0/+4
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add generic vector ops for constant shiftsRichard Henderson2018-02-081-0/+29
| | | | | | | | | Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add types and basic operations for host vectorsRichard Henderson2018-02-081-0/+49
| | | | | | | Nothing uses or enables them yet. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* docs: fix broken paths to docs/devel/atomics.txtPhilippe Mathieu-Daudé2017-07-311-1/+1
| | | | | | | | With the move of some docs/ to docs/devel/ on ac06724a71, a couple of references were not updated. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg: Introduce goto_ptr opcode and tcg_gen_lookup_and_goto_ptrEmilio G. Cota2017-06-051-0/+8
| | | | | | | | | | | | | | | | | | Instead of exporting goto_ptr directly to TCG frontends, export tcg_gen_lookup_and_goto_ptr(), which calls goto_ptr with the pointer returned by the lookup_tb_ptr() helper. This is the only use case we have for goto_ptr and lookup_tb_ptr, so having this function is very convenient. Furthermore, it trivially allows us to avoid calling the lookup helper if goto_ptr is not implemented by the backend. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1493263764-18657-2-git-send-email-cota@braap.org> Message-Id: <1493263764-18657-3-git-send-email-cota@braap.org> Message-Id: <1493263764-18657-4-git-send-email-cota@braap.org> Message-Id: <1493263764-18657-5-git-send-email-cota@braap.org> [rth: Squashed 4 related commits.] Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add clz and ctz opcodesRichard Henderson2017-01-101-0/+8
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Allow an operand to be matching or a constantRichard Henderson2017-01-101-4/+9
| | | | | | | | This allows an output operand to match an input operand only when the input operand needs a register. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add field extraction primitivesRichard Henderson2017-01-101-2/+18
| | | | | | | | Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* qemu-tech: move text from qemu-tech to tcg/READMEPaolo Bonzini2016-10-071-0/+5
| | | | | Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Introduce TCGOpcode for memory barrierPranith Kumar2016-09-161-0/+17
| | | | | | | | | | | This commit introduces the TCGOpcode for memory barrier instruction. This opcode takes an argument which is the type of memory barrier which should be generated. Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-2-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Fix some typos found by codespellStefan Weil2016-05-181-1/+1
| | | | | | Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg: Rename tcg-target.c to tcg-target.inc.cPeter Maydell2016-02-231-2/+3
| | | | | | | | | | | Rename the per-architecture tcg-target.c files to tcg-target.inc.c. This makes it clearer that they are not intended to be standalone C files, but are instead #included into another source file. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1456238983-10160-2-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson2015-08-241-4/+10
| | | | | | | Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: update README about size changing opsAurelien Jarno2015-08-241-3/+15
| | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: rename trunc_shr_i32 into trunc_shr_i64_i32Aurelien Jarno2015-08-241-1/+1
| | | | | | | | | | | The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32, and the name in the README doesn't match the name offered to the frontends. Always use the long name to make it clear it is a size changing op. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add INDEX_op_trunc_shr_i32Richard Henderson2014-04-281-0/+5
| | | | | | Let the backend do something special for truncation. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Use "unspecified behavior" for shiftsRichard Henderson2014-04-191-5/+13
| | | | | | | | Change the definition such that shifts are not allowed to crash for any input. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add qemu_ld_st_i32/64Richard Henderson2013-10-101-24/+19Star
| | | | | | | Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Use proper term in TCG README陳韋任 (Wei-Ren Chen)2013-03-221-5/+9
| | | | | | | | | | In TCG, "target" means the host architecture for which TCG generates the code. Using "guest" rather than "target" to make the document more consistent. Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* tcg: Add signed multiword multiplication operationsRichard Henderson2013-02-231-0/+4
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Add 64-bit multiword arithmetic operationsRichard Henderson2013-02-231-12/+14
| | | | | | Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: rework TCG helper flagsAurelien Jarno2012-10-281-5/+14
| | | | | | | | | | | | | | | | | | | | | | | The current helper flags, TCG_CALL_CONST and TCG_CALL_PURE might be confusing and doesn't provide enough granularity for some helpers (FP helpers for example). This patch changes them into the following helpers flags: - TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals, either directly or via an exception. They will not be saved to their canonical location before calling the helper. - TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals. They will only be saved to their canonical locations before calling helpers, but they won't be reloaded afterwise. - TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if the return value is not used. It provides convenience flags, to avoid helper definitions longer than 80 characters. It also provides compatibility flags, and updates the documentation. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: forbid ld/st function to modify globalsAurelien Jarno2012-10-281-0/+3
| | | | | | | | | | | Mapping a memory address using a global and accessing it through ld/st operations is currently broken. As it doesn't make any sense to do that performance wise, let's forbid that. Update the TCG documentation, and remove partial support for that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: remove obsolete jmp opAurelien Jarno2012-10-061-6/+1Star
| | | | | | | | | | | | | The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Adjust descriptions of *cond opcodesRichard Henderson2012-09-261-5/+5
| | | | | | | | | | The README file documented the operand ordering of the tcg_gen_* functions. Since we're documenting opcodes here, use the true operand ordering. Signed-off-by: Richard Henderson <rth@twiddle.net> Cc: malc <av1474@comtv.ru> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/README: document tcg_gen_goto_tb restrictionsMax Filippov2012-09-221-1/+2
| | | | | | | | | See http://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.html for the whole story. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Introduce movcondRichard Henderson2012-09-211-0/+6
| | | | | | | | Implemented with setcond if the target does not provide the optional opcode. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/README: Expand advice on number of TCG ops per target insnPeter Maydell2011-07-161-1/+9
| | | | | | | | | Expand the note on the number of TCG ops generated per target insn, to be clearer about the range of applicability of the 20 op rule of thumb. Also add a note about the hard MAX_OP_PER_INSTR limit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: README, name deposit second argument len/LENEdgar E. Iglesias2011-01-201-2/+2
| | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* tcg: Define "deposit" as an optional operation.Richard Henderson2011-01-201-0/+14
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* tcg: fix typo in readmeMike Frysinger2011-01-091-1/+1
| | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/README: Spelling fixesStefan Weil2011-01-091-4/+4
| | | | | Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg/README: improve description of bswap*Aurelien Jarno2010-04-101-4/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson2010-03-261-3/+7
| | | | | | | | | | | | | | | Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: Allow target-specific implementation of EQV.Richard Henderson2010-03-261-1/+1
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: update README with const and pure helpersAurelien Jarno2010-03-131-4/+7
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: generic support for conditional setRichard Henderson2010-02-061-0/+13
| | | | | | | Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg: document double-word support opcodes.Richard Henderson2010-02-061-0/+23
| | | | | | | | | The internal opcodes brcond2, add2, sub2, mulu2 were undocumented. Place these in a new section that clearly indicates that they are not to be emitted by translators. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tcg/README: fix description of bswap32_i32/i64aurel322009-03-291-1/+1
| | | | | | | | Thanks to Stuart Brady for the notice. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6920 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: update README wrt recent bswap changesaurel322009-03-131-6/+7
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6834 c046a42c-6fe2-441c-8c8c-71466251a162
* TCG: Fix documentation of qemu_ld/st opsaurel322009-01-031-11/+11
| | | | | | | | | | | The functions defined in tcg/tcg-op.h have no _i32 or _i64 suffix, qemu_ld64 and qemu_st64 were missing from the list, and there are no 'plain' qemu_ld/qemu_st ops. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6148 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove a few dyngen and dyngen related codeaurel322008-12-071-17/+4Star
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5914 c046a42c-6fe2-441c-8c8c-71466251a162
* Mention output overlaps.pbrook2008-11-041-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5619 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg-ops.h: add rotl/rotli and rotr/rotri TCG instructionsaurel322008-11-031-1/+9
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5607 c046a42c-6fe2-441c-8c8c-71466251a162
* TCG: add logical operations found on alpha and powerpc processorsaurel322008-10-211-0/+20
| | | | | | | | | | | | - andc_i32/i64 t0, t1, t2 - eqv_i32/i64 t0, t1, t2 - nand_i32/i64 t0, t1, t2 - nor_i32/i64 t0, t1, t2 - orc_i32/i64 t0, t1, t2 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5501 c046a42c-6fe2-441c-8c8c-71466251a162