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path: root/target/arm/cpu.h
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* target/arm: Add ARM_FEATURE_V8_FCMARichard Henderson2018-03-021-0/+1
* target/arm: Add ARM_FEATURE_V8_RDMRichard Henderson2018-03-021-0/+1
* target/arm: Define init-svtor property for the reset secure VTOR valuePeter Maydell2018-03-021-0/+3
* target/arm: Define an IDAU interfacePeter Maydell2018-03-021-0/+3
* target/arm/cpu.h: add additional float_status flagsAlex Bennée2018-03-011-7/+25
* target/arm/cpu.h: update comment for half-precision valuesAlex Bennée2018-03-011-0/+1
* target/arm/cpu64: introduce ARM_V8_FP16 feature bitAlex Bennée2018-03-011-0/+1
* target/*/cpu.h: remove softfloat.hAlex Bennée2018-02-211-2/+0Star
* target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell2018-02-151-0/+2
* hw/intc/armv7m_nvic: Implement SCRPeter Maydell2018-02-151-0/+7
* hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell2018-02-151-0/+26
* target/arm: Enforce access to ZCR_EL at translationRichard Henderson2018-02-151-1/+2
* target/arm: Enforce FP access to FPCR/FPSRRichard Henderson2018-02-151-17/+18
* target/arm: Add SVE state to TB->FLAGSRichard Henderson2018-02-091-0/+8
* target/arm: Add ZCR_ELxRichard Henderson2018-02-091-0/+5
* target/arm: Add predicate registers for SVERichard Henderson2018-02-091-0/+12
* target/arm: Expand vector registers for SVERichard Henderson2018-02-091-19/+40
* target/arm: implement SM4 instructionsArd Biesheuvel2018-02-091-0/+1
* target/arm: implement SM3 instructionsArd Biesheuvel2018-02-091-0/+1
* target/arm: implement SHA-3 instructionsArd Biesheuvel2018-02-091-0/+1
* target/arm: implement SHA-512 instructionsArd Biesheuvel2018-02-091-0/+1
* target/arm: Split "get pending exception info" from "acknowledge it"Peter Maydell2018-02-091-3/+16
* target/arm: Add armv7m_nvic_set_pending_derived()Peter Maydell2018-02-091-0/+13
* target/arm: Align vector registersRichard Henderson2018-02-081-1/+1
* target/arm: Move cpu_get_tb_cpu_state out of lineRichard Henderson2018-01-251-125/+2Star
* target/arm: Add ARM_FEATURE_SVERichard Henderson2018-01-251-0/+1
* target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpersRichard Henderson2018-01-251-0/+27
* target/arm: Change the type of vfp.regsRichard Henderson2018-01-251-1/+1
* target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()Peter Maydell2017-12-131-5/+16
* target/arm: Split M profile MNegPri mmu index into user and privPeter Maydell2017-12-131-21/+33
* target/arm: Factor out "get mmuidx for specified security state"Peter Maydell2017-10-061-11/+21
* target/arm: Fix calculation of secure mm_idx valuesPeter Maydell2017-10-061-5/+7
* nvic: Implement Security Attribution Unit registersPeter Maydell2017-10-061-0/+10
* target/arm: Add new-in-v8M SFSR and SFARPeter Maydell2017-10-061-0/+12
* target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler modePeter Maydell2017-10-061-1/+7
* nvic: Support banked exceptions in acknowledge and completePeter Maydell2017-09-211-2/+13
* target/arm: Handle banking in negative-execution-priority check in cpu_mmu_in...Peter Maydell2017-09-211-5/+16
* nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell2017-09-211-1/+13
* nvic: Implement AIRCR changes for v8MPeter Maydell2017-09-211-0/+12
* arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directlyIgor Mammedov2017-09-191-0/+3
* target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2Peter Maydell2017-09-141-16/+19
* target/arm: Add Jazelle featurePortia Stephens2017-09-071-0/+1
* target/arm: Implement BXNS, and banked stack pointersPeter Maydell2017-09-071-0/+13
* target/arm: Make CFSR register banked for v8MPeter Maydell2017-09-071-1/+6
* target/arm: Make MMFAR banked for v8MPeter Maydell2017-09-071-1/+1
* target/arm: Make CCR register banked for v8MPeter Maydell2017-09-071-1/+1
* target/arm: Make MPU_CTRL register banked for v8MPeter Maydell2017-09-071-1/+1
* target/arm: Make MPU_RNR register banked for v8MPeter Maydell2017-09-071-1/+1
* target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell2017-09-071-2/+2
* target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8MPeter Maydell2017-09-071-2/+2
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