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* target/mips: Remove unused CPUMIPSState* from MXU functionsPhilippe Mathieu-Daudé2021-03-131-10/+10
* target/mips: Remove XBurst Media eXtension Unit dead codePhilippe Mathieu-Daudé2021-03-131-1286/+0Star
* target/mips: Rewrite complex ifdef'ryPhilippe Mathieu-Daudé2021-03-131-4/+7
* target/mips/meson: Restrict mips-semi.c to TCGPhilippe Mathieu-Daudé2021-03-131-1/+1
* target/mips/meson: Introduce mips_tcg source setPhilippe Mathieu-Daudé2021-03-131-2/+5
* Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...Peter Maydell2021-03-111-2/+2
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| * sysemu: Let VMChangeStateHandler take boolean 'running' argumentPhilippe Mathieu-Daudé2021-03-091-2/+2
* | Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda...Peter Maydell2021-03-113-4/+4
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| * | semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-103-4/+4
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* / clock: Add ClockEvent parameter to callbacksPeter Maydell2021-03-081-1/+1
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* target/mips: Use GPR move functions in gen_HILO1_tx79()Philippe Mathieu-Daudé2021-02-211-17/+4Star
* target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé2021-02-212-0/+22
* target/mips: Rename 128-bit upper halve GPR registersPhilippe Mathieu-Daudé2021-02-211-1/+3
* target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé2021-02-213-27/+34
* target/mips: Make cpu_HI/LO registers publicPhilippe Mathieu-Daudé2021-02-212-1/+2
* target/mips: Include missing "tcg/tcg.h" headerPhilippe Mathieu-Daudé2021-02-211-0/+1
* target/mips: Remove unused 'rw' argument from page_table_walk_refill()Philippe Mathieu-Daudé2021-02-211-3/+3
* target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessTypePhilippe Mathieu-Daudé2021-02-212-10/+10
* target/mips: Let get_seg*_physical_address() take MMUAccessType argPhilippe Mathieu-Daudé2021-02-211-5/+6
* target/mips: Let get_physical_address() take MMUAccessType argumentPhilippe Mathieu-Daudé2021-02-211-10/+10
* target/mips: Let raise_mmu_exception() take MMUAccessType argumentPhilippe Mathieu-Daudé2021-02-211-5/+5
* target/mips: Let cpu_mips_translate_address() take MMUAccessType argPhilippe Mathieu-Daudé2021-02-212-4/+4
* target/mips: Let do_translate_address() take MMUAccessType argumentPhilippe Mathieu-Daudé2021-02-211-3/+4
* target/mips: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé2021-02-212-2/+2
* target/mips: Remove unused MMU definitionsPhilippe Mathieu-Daudé2021-02-211-16/+0Star
* target/mips: Remove access_type argument from get_physical_address()Philippe Mathieu-Daudé2021-02-211-13/+9Star
* target/mips: Remove access_type arg from get_segctl_physical_address()Philippe Mathieu-Daudé2021-02-211-10/+10
* target/mips: Remove access_type argument from get_seg_physical_addressPhilippe Mathieu-Daudé2021-02-211-3/+3
* target/mips: Remove access_type argument from map_address() handlerPhilippe Mathieu-Daudé2021-02-212-12/+11Star
* target/mips: fetch code with translator_ldPhilippe Mathieu-Daudé2021-02-211-10/+10
* target/mips: Create mips_io_recompile_replay_branchRichard Henderson2021-02-181-0/+18
* sev/i386: Don't allow a system reset under an SEV-ES guestTom Lendacky2021-02-161-0/+5
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-13/+23
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+2
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-1/+3
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-2/+2
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+3
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé2021-01-142-10/+7Star
* target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé2021-01-142-5/+2Star
* target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé2021-01-141-1/+0Star
* target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+2
* target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
* target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+8
* target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+5
* target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+6
* target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
* target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé2021-01-142-1/+2
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