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path: root/target/riscv/translate.c
Commit message (Expand)AuthorAgeFilesLines
* riscv: Add semihosting supportKeith Packard2021-01-181-0/+11
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-101-0/+2
* target/riscv: Update the Hypervisor trap return/entryAlistair Francis2020-08-251-10/+0Star
* target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson2020-08-221-0/+18
* target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson2020-08-221-0/+11
* meson: targetPaolo Bonzini2020-08-211-2/+2
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-10/+10
* target/riscv: add vector stride load and store instructionsLIU Zhiwei2020-07-021-0/+7
* target/riscv: add vector configure instructionLIU Zhiwei2020-07-021-2/+15
* target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei2020-07-021-1/+2
* target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis2020-06-191-0/+1
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-271-1/+1
* target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis2020-02-271-1/+15
* target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis2020-02-271-0/+13
* target/riscv: Print priv and virt in disas logAlistair Francis2020-02-271-0/+8
* target/riscv: progressively load the instruction during decodeAlex Bennée2020-02-251-19/+21
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...Peter Maydell2020-01-241-1/+1
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| * target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung2020-01-161-1/+1
* | tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
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* remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata2019-11-141-3/+1Star
* target/riscv: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
* target/riscv: Remove redundant declaration pragmasRichard Henderson2019-08-191-18/+1Star
* RISC-V: Add support for the Zifencei extensionPalmer Dabbelt2019-06-261-0/+3
* target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-241-2/+17
* target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson2019-05-241-1/+0Star
* target/riscv: Merge argument decode for RVC shiftiRichard Henderson2019-05-241-0/+6
* target/riscv: Use --static-decode for decodetreeRichard Henderson2019-05-241-3/+0Star
* target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson2019-05-241-0/+18
* RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-241-5/+25
* decodetree: Add DisasContext argument to !function expandersRichard Henderson2019-05-061-2/+2
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt2019-03-221-0/+21
* target/riscv: Remove decode_RV32_64G()Bastian Koppelmann2019-03-131-20/+1Star
* target/riscv: Remove gen_system()Bastian Koppelmann2019-03-131-34/+0Star
* target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-131-2/+2
* target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-131-187/+133Star
* target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-131-41/+18Star
* target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-131-15/+25
* target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-131-80/+27Star
* target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-131-3/+5
* target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-131-2/+4
* target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-131-47/+0Star
* target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-131-38/+0Star
* target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-81/+2Star
* target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-117/+1Star
* target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-37/+16Star
* target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann2019-03-131-56/+1Star
* target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann2019-03-131-600/+1Star
* target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann2019-03-131-0/+1
* target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann2019-03-131-0/+1
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