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path: root/target/xtensa/translate.c
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* target/xtensa: fix FPU2000 bugsMax Filippov2018-09-171-3/+3
* target/xtensa: Convert to TranslatorOpsRichard Henderson2018-06-301-101/+116
* target/xtensa: Change gen_intermediate_code dc to pointerRichard Henderson2018-06-301-61/+61
* target/xtensa: Convert to DisasContextBaseRichard Henderson2018-06-301-47/+44Star
* target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURNRichard Henderson2018-06-301-12/+9Star
* target/xtensa: check zero overhead loop alignmentMax Filippov2018-06-301-0/+7
* target/xtensa: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé2018-06-081-3/+3
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-2/+2
* Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into st...Peter Maydell2018-05-211-5/+2Star
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| * Remove unnecessary variables for function return valueLaurent Vivier2018-05-201-5/+2Star
* | target/xtensa: Honor CPU_DUMP_FPURichard Henderson2018-05-181-1/+2
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* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell2018-05-111-17/+33
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| * target/xtensa: Use new min/max expandersRichard Henderson2018-05-101-17/+33
* | target/xtensa: avoid integer overflow in next_page PC checkEmilio G. Cota2018-05-091-5/+4Star
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* target/xtensa: add linux-user supportMax Filippov2018-03-161-6/+37
* target/xtensa: support MTTCGMax Filippov2018-03-131-15/+31
* target/xtensa: mark register windows in the dumpMax Filippov2018-03-131-2/+7
* target/xtensa: dump correct physical registersMax Filippov2018-03-131-0/+1
* Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into stagingPeter Maydell2018-01-241-2/+2
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| * target/xtensa: disas/xtensa: fix coverity warningsMax Filippov2018-01-221-2/+2
* | target/xtensa: Remove duplicate typedef of DisasContextPeter Maydell2018-01-121-2/+2
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* target/xtensa: implement const16Max Filippov2018-01-091-0/+14
* target/xtensa: implement GPIO32Max Filippov2018-01-091-0/+53
* target/xtensa: implement salt/saltuMax Filippov2018-01-091-0/+18
* target/xtensa: add internal/noop SRs and opcodesMax Filippov2018-01-091-0/+33
* target/xtensa: drop DisasContext::litbaseMax Filippov2018-01-091-22/+5Star
* target/xtensa: use libisa for instruction decodingMax Filippov2018-01-091-2144/+84Star
* target/xtensa: extract FPU2000 opcode translatorsMax Filippov2017-12-191-0/+374
* target/xtensa: extract core opcode translatorsMax Filippov2017-12-191-0/+3121
* target/xtensa: pass actual frame size to the entry helperMax Filippov2017-12-191-1/+1
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-3/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-14/+14
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* target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova2017-09-061-0/+4
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+2Star
* Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into stagingPeter Maydell2017-01-251-78/+167
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| * target-xtensa: implement RER/WER instructionsMax Filippov2017-01-171-2/+10
| * target/xtensa: implement MEMCTL SRMax Filippov2017-01-151-0/+8
| * target/xtensa: don't continue translation after exceptionMax Filippov2017-01-151-1/+4
| * target/xtensa: support icountMax Filippov2017-01-151-45/+134
| * target/xtensa: refactor CCOUNT/CCOMPAREMax Filippov2017-01-151-31/+12Star
* | target-xtensa: Use clrsb helperRichard Henderson2017-01-101-10/+1Star
* | target-xtensa: Use clz opcodeRichard Henderson2017-01-101-2/+11
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* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+3225
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