summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_reg.h
Commit message (Expand)AuthorAgeFilesLines
* drm/i915/skl: Implementation of SKL display power well supportSatheeshakrishna M2015-02-131-0/+20
* drm/i915/skl: Enabling PSR on SkylakeSonika Jindal2015-01-281-0/+5
* drm/i915/skl: Gen9 coarse power gatingZhe Wang2015-01-271-0/+3
* drm/i915: New offset for reading frequencies on CHV.Deepak S2015-01-271-0/+9
* drm/i915/chv: Populate total EU count on CherryviewDeepak S2015-01-271-0/+11
* drm/i915: Improve HiZ throughput on Cherryview.Kenneth Graunke2015-01-131-0/+3
* Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queuedDaniel Vetter2015-01-121-3/+18
|\
| * drm/i915: Disable PSMI sleep messages on all rings around context switchesChris Wilson2014-12-161-0/+2
| * drm/i915: Invalidate media caches on gen7Chris Wilson2014-12-161-0/+1
| * drm/i915: save/restore GMBUS freq across suspend/resume on gen4Jesse Barnes2014-12-111-0/+1
| * drm/i915/bdw: Fix the write setting up the WIZ hashing modeDamien Lespiau2014-12-101-3/+14
* | drm/i915: Make sample_c messages go faster on Haswell.Kenneth Graunke2015-01-061-0/+1
* | drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelistJordan Justen2014-12-161-11/+12
* | drm/i915: Engage the DP scramble reset for pipe C on CHVVille Syrjälä2014-12-101-1/+2
* | drm/i915: Add MI_SET_APPID cmd to cmd parser tablesMichael H. Nguyen2014-12-101-0/+3
* | drm/i915: Pixel Clock changes for DSI dual linkGaurav K Singh2014-12-051-0/+4
* | drm/i915: Add support for port enable/disable for dual link configurationGaurav K Singh2014-12-051-0/+1
* | drm/i915: s/MI_STORE_DWORD_IMM_GEN8/MI_STORE_DWORD_IMM_GEN4/Ville Syrjälä2014-12-051-2/+3
* | drm/i915/dsi: clean up MIPI DSI pipe vs. port usageJani Nikula2014-12-031-150/+153
* | drm/i915: Add PSR registers for PSR VLV/CHV.Rodrigo Vivi2014-12-031-0/+36
|/
* drm/i915: Implement GPU reset for 915/945Ville Syrjälä2014-12-031-1/+1
* drm/i915: Fix gen4 GPU resetVille Syrjälä2014-12-031-0/+1
* drm/i915: Pin tiled objects for L-shaped configsDaniel Vetter2014-11-201-0/+2
* drm/i915: Use efficient frequency for HSW/BDWTom O'Rourke2014-11-201-0/+1
* drm/i915: Drop the HSW special case from __gen6_gt_wait_for_thread_c0()Ville Syrjälä2014-11-171-1/+0Star
* drm/i915: Add a name for the Punit GPLLENABLE bitVille Syrjälä2014-11-171-0/+1
* drm/i915: Clear PCODE_DATA1 on SNB+Damien Lespiau2014-11-141-1/+1
* drm/i915/skl: AUX irqs have movedJesse Barnes2014-11-141-0/+3
* drm/i915/skl: fetch, enable/disable pfit as needed v2Jesse Barnes2014-11-141-0/+12
* drm/i915/skl: Implement queue_flipDamien Lespiau2014-11-141-0/+10
* drm/i915/skl: Determine enabled PLL and its linkrate/pixel clockSatheeshakrishna M2014-11-141-0/+5
* drm/i915/skl: Register definitions for SKL ClocksSatheeshakrishna M2014-11-141-0/+72
* drm/i915: Add the predicate source registers to the register whitelistNeil Roberts2014-11-141-0/+2
* drm/i915/chv: Add new workarounds for chvArun Siluvery2014-11-141-0/+1
* Merge remote-tracking branch 'airlied/drm-next' into HEADDaniel Vetter2014-11-101-1/+1
|\
| * Merge tag 'topic/core-stuff-2014-11-05' of git://anongit.freedesktop.org/drm-...Dave Airlie2014-11-071-1/+1
| |\
| | * gpu:drm: Fix typo in Documentation/DocBook/drm.xmlMasanari Iida2014-10-211-1/+1
* | | drm/i915: make pipe/port based audio valid accessors easier to useJani Nikula2014-11-071-14/+6Star
* | | drm/i915/skl: Gen9 ForcewakeZhe Wang2014-11-071-0/+6
* | | drm/i915/skl: Program the DDB allocationDamien Lespiau2014-11-071-0/+16
* | | drm/i915/skl: Register definitions and macros for SKL Watermark regsPradeep Bhat2014-11-071-0/+35
* | | drm/i915/skl: Read the Memory Latency Values for WM computationPradeep Bhat2014-11-071-0/+7
* | | drm/i915: clean up and clarify audio related register definesJani Nikula2014-11-071-82/+83
* | | drm/i915: Add support for CHV pipe B sprite CSCVille Syrjälä2014-11-041-0/+33
* | | drm/i915: Initialize new chv primary plane and pipe blender registersVille Syrjälä2014-11-041-1/+24
|/ /
* | drm/i915: Add rotation support for cursor plane (v5)Ville Syrjälä2014-10-241-0/+1
* | drm/i915/chv: Use 16 and 32 for low and high drain latency precision.Rodrigo Vivi2014-10-241-6/+7
* | drm/i915: Fix chv PCS DW11 register definesVille Syrjälä2014-10-241-2/+2
* | drm/i915/skl: Add 180 degree HW rotation supportSonika Jindal2014-10-241-0/+3
* | Merge branch 'drm-intel-next-fixes' into drm-intel-nextDaniel Vetter2014-10-211-4/+3Star
|\ \