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path: root/include/hw/riscv
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* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-3/+3
* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-181-6/+17
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-3/+5
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-3/+5
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-181-6/+0Star
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-181-6/+0Star
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-181-0/+3
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-1/+4
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-0/+2
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-1/+3
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+5
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-0/+3
* hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis2020-10-221-0/+2
* hw/riscv: Return the end address of the loaded firmwareAlistair Francis2020-10-221-4/+4
* hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis2020-10-221-0/+1
* Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost2020-09-182-6/+2Star
* sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-17/+17
* sifive_e: Rename memmap enum constantsEduardo Habkost2020-09-181-19/+19
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-1313-642/+149Star
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| * hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-101-45/+0Star
| * hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-101-77/+0Star
| * hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-101-59/+0Star
| * hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-81/+0Star
| * hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-60/+0Star
| * hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-103-78/+2Star
| * hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-102-81/+1Star
| * hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-102-92/+1Star
| * hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-101-71/+0Star
| * hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-101-0/+11
| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+3
| * hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+3
| * hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+7
| * hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-101-0/+11
| * hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-101-0/+4
| * hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-101-0/+20
| * hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-101-0/+88
| * hw/riscv: hart: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+1
* | Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-094-8/+8
* | Move QOM typedefs and add missing includesEduardo Habkost2020-09-094-8/+16
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* opentitan: Rename memmap enum constantsEduardo Habkost2020-08-271-19/+19
* hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel2020-08-251-2/+7
* hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel2020-08-251-2/+9
* hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel2020-08-251-0/+113
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-5/+7
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-3/+4
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-221-0/+4
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-142-1/+62
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-141-1/+3
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