| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16 | Richard Henderson | 2021-06-03 | 1 | -0/+15 |
| * | target/arm: Allow board models to specify initial NS VTOR | Peter Maydell | 2021-06-03 | 1 | -0/+2 |
| * | target/arm: Make FPSCR.LTPSIZE writable for MVE | Peter Maydell | 2021-06-03 | 1 | -1/+2 |
| * | target/arm: Implement M-profile VPR register | Peter Maydell | 2021-06-03 | 1 | -0/+6 |
| * | target/arm: Add isar feature check functions for MVE | Peter Maydell | 2021-06-03 | 1 | -0/+22 |
| * | target/arm: Implement aarch32 VSUDOT, VUSDOT | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement aarch64 SUDOT, USDOT | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 crypto constructive binary operations | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 crypto destructive binary operations | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE mixed sign dot product (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 FMMLA | Stephen Long | 2021-05-25 | 1 | -0/+10 |
| * | target/arm: Implement SVE2 bitwise permute | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 PMULLB, PMULLT | Richard Henderson | 2021-05-25 | 1 | -0/+10 |
| * | target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Add support for FEAT_TLBIOS | Rebecca Cran | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Add support for FEAT_TLBIRANGE | Rebecca Cran | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Add ALIGN_MEM to TBFLAG_ANY | Richard Henderson | 2021-04-30 | 1 | -0/+2 |
| * | target/arm: Move TBFLAG_ANY bits to the bottom | Richard Henderson | 2021-04-30 | 1 | -7/+7 |
| * | target/arm: Move TBFLAG_AM32 bits to the top | Richard Henderson | 2021-04-30 | 1 | -21/+21 |
| * | target/arm: Move mode specific TB flags to tb->cs_base | Richard Henderson | 2021-04-30 | 1 | -21/+28 |
| * | target/arm: Introduce CPUARMTBFlags | Richard Henderson | 2021-04-30 | 1 | -11/+15 |
| * | target/arm: Add wrapper macros for accessing tbflags | Richard Henderson | 2021-04-30 | 1 | -1/+21 |
| * | target/arm: Rename TBFLAG_ANY, PSTATE_SS | Richard Henderson | 2021-04-30 | 1 | -1/+1 |
| * | target/arm: Rename TBFLAG_A32, SCTLR_B | Richard Henderson | 2021-04-30 | 1 | -1/+1 |
| * | Revert "target/arm: Make number of counters in PMCR follow the CPU" | Peter Maydell | 2021-04-06 | 1 | -1/+0 |
| * | target/arm: Make number of counters in PMCR follow the CPU | Peter Maydell | 2021-03-30 | 1 | -0/+1 |
| * | target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe | Rebecca Cran | 2021-03-05 | 1 | -1/+14 |
| * | linux-user/aarch64: Implement PROT_MTE | Richard Henderson | 2021-02-16 | 1 | -0/+1 |
| * | linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE | Richard Henderson | 2021-02-16 | 1 | -0/+31 |
| * | target/arm: Add support for FEAT_DIT, Data Independent Timing | Rebecca Cran | 2021-02-11 | 1 | -0/+12 |
| * | target/arm: Fix SCR RES1 handling | Mike Nawrocki | 2021-02-11 | 1 | -0/+5 |
| * | target/arm: Implement ID_PFR2 | Richard Henderson | 2021-01-29 | 1 | -0/+1 |
| * | target/arm: Implement SCR_EL2.EEL2 | Rémi Denis-Courmont | 2021-01-19 | 1 | -2/+6 |
| * | target/arm: set HPFAR_EL2.NS on secure stage 2 faults | Rémi Denis-Courmont | 2021-01-19 | 1 | -0/+2 |
| * | target/arm: secure stage 2 translation regime | Rémi Denis-Courmont | 2021-01-19 | 1 | -1/+5 |
| * | target/arm: add ARMv8.4-SEL2 system registers | Rémi Denis-Courmont | 2021-01-19 | 1 | -0/+7 |
| * | target/arm: add MMU stage 1 for Secure EL2 | Rémi Denis-Courmont | 2021-01-19 | 1 | -14/+23 |
| * | target/arm: Define isar_feature function to test for presence of SEL2 | Rémi Denis-Courmont | 2021-01-19 | 1 | -0/+5 |
| * | target/arm: use arm_is_el2_enabled() where applicable | Rémi Denis-Courmont | 2021-01-19 | 1 | -2/+2 |
| * | target/arm: add arm_is_el2_enabled() helper | Rémi Denis-Courmont | 2021-01-19 | 1 | -0/+17 |
| * | target/arm: Add cpu properties to control pauth | Richard Henderson | 2021-01-19 | 1 | -0/+10 |
| * | target/arm: Implement an IMPDEF pauth algorithm | Richard Henderson | 2021-01-19 | 1 | -4/+11 |
| * | semihosting: Change common-semi API to be architecture-independent | Keith Packard | 2021-01-18 | 1 | -8/+0 |
| * | target/arm: add aarch32 ID register fields to cpu.h | Leif Lindholm | 2021-01-12 | 1 | -0/+28 |
| * | target/arm: add aarch64 ID register fields to cpu.h | Leif Lindholm | 2021-01-12 | 1 | -0/+15 |
| * | target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h | Leif Lindholm | 2021-01-12 | 1 | -0/+31 |
| * | target/arm: make ARMCPU.ctr 64-bit | Leif Lindholm | 2021-01-12 | 1 | -1/+1 |
| * | target/arm: make ARMCPU.clidr 64-bit | Leif Lindholm | 2021-01-12 | 1 | -1/+1 |
| * | target/arm: fix typo in cpu.h ID_AA64PFR1 field name | Leif Lindholm | 2021-01-12 | 1 | -1/+1 |
| * | target/arm: ARMv8.4-TTST extension | Rémi Denis-Courmont | 2021-01-12 | 1 | -0/+5 |
