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* target/riscv: Add checks for several RVC reserved operandsRichard Henderson2019-05-242-3/+14
* target/riscv: Add the HGATP register masksAlistair Francis2019-05-241-0/+11
* target/riscv: Add the HSTATUS register masksAlistair Francis2019-05-241-0/+18
* target/riscv: Add Hypervisor CSR macrosAlistair Francis2019-05-241-3/+6
* target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis2019-05-241-9/+8Star
* target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis2019-05-241-3/+2Star
* target/riscv: Improve the scause logicAlistair Francis2019-05-241-1/+1
* target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2019-05-242-8/+27
* target/riscv: Mark privilege level 2 as reservedAlistair Francis2019-05-241-1/+1
* target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-242-0/+16
* target/riscv: Create settable CPU propertiesAlistair Francis2019-05-242-0/+57
* target/riscv: Remove spaces from register namesRichard Henderson2019-05-241-8/+8
* target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-242-9/+24
* target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson2019-05-246-151/+67Star
* target/riscv: Use pattern groups in insn16.decodeRichard Henderson2019-05-243-69/+29Star
* target/riscv: Merge argument decode for RVC shiftiRichard Henderson2019-05-243-53/+12Star
* target/riscv: Merge argument sets for insn32 and insn16Richard Henderson2019-05-242-170/+58Star
* target/riscv: Use --static-decode for decodetreeRichard Henderson2019-05-242-7/+4Star
* target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson2019-05-242-3/+25
* RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-243-12/+32
* target/riscv: Do not allow sfence.vma from user modeJonathan Behrens2019-05-241-3/+4
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into stagingPeter Maydell2019-05-163-35/+25Star
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| * tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson2019-05-101-6/+0Star
| * target/riscv: Convert to CPUClass::tlb_fillRichard Henderson2019-05-103-30/+26Star
* | Clean up ill-advised or unusual header guardsMarkus Armbruster2019-05-131-2/+2
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* decodetree: Add DisasContext argument to !function expandersRichard Henderson2019-05-062-7/+7
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-19/+18Star
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-182-14/+5Star
* target/riscv: Fix wrong expanding for c.fswspKito Cheng2019-03-261-1/+1
* target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt2019-03-222-2/+23
* target/riscv: Remove unused structAlistair Francis2019-03-191-6/+0Star
* RISC-V: Update load reservation comment in do_interruptMichael Clark2019-03-191-1/+7
* RISC-V: Convert trap debugging to trace eventsMichael Clark2019-03-192-9/+5Star
* RISC-V: Add support for vectored interruptsMichael Clark2019-03-192-97/+60Star
* RISC-V: Change local interrupts from edge to levelMichael Clark2019-03-191-2/+2
* RISC-V: linux-user support for RVE ABIKito Cheng2019-03-192-1/+6
* RISC-V: Allow interrupt controllers to claim interruptsMichael Clark2019-03-193-8/+15
* riscv: pmp: Log pmp access errors as guest errorsAlistair Francis2019-03-191-7/+13
* RISC-V: Add hooks to use the gdb xml files.Jim Wilson2019-03-193-12/+349
* RISC-V: Add debug support for accessing CSRs.Jim Wilson2019-03-192-7/+30
* RISC-V: Fixes to CSR_* register macros.Jim Wilson2019-03-191-2/+33
* target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann2019-03-181-5/+25
* target/riscv: Remove decode_RV32_64G()Bastian Koppelmann2019-03-131-20/+1Star
* target/riscv: Remove gen_system()Bastian Koppelmann2019-03-131-34/+0Star
* target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-133-18/+18
* target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-132-211/+164Star
* target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-132-71/+81
* target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-133-30/+34
* target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-133-100/+108
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