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path: root/target/arm/cpu.h
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* target/arm: Implement SVE2 FMMLAStephen Long2021-05-251-0/+10
* target/arm: Implement SVE2 bitwise permuteRichard Henderson2021-05-251-0/+5
* target/arm: Implement SVE2 PMULLB, PMULLTRichard Henderson2021-05-251-0/+10
* target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2Richard Henderson2021-05-251-0/+16
* target/arm: Add support for FEAT_TLBIOSRebecca Cran2021-05-251-0/+5
* target/arm: Add support for FEAT_TLBIRANGERebecca Cran2021-05-251-0/+5
* target/arm: Add ALIGN_MEM to TBFLAG_ANYRichard Henderson2021-04-301-0/+2
* target/arm: Move TBFLAG_ANY bits to the bottomRichard Henderson2021-04-301-7/+7
* target/arm: Move TBFLAG_AM32 bits to the topRichard Henderson2021-04-301-21/+21
* target/arm: Move mode specific TB flags to tb->cs_baseRichard Henderson2021-04-301-21/+28
* target/arm: Introduce CPUARMTBFlagsRichard Henderson2021-04-301-11/+15
* target/arm: Add wrapper macros for accessing tbflagsRichard Henderson2021-04-301-1/+21
* target/arm: Rename TBFLAG_ANY, PSTATE_SSRichard Henderson2021-04-301-1/+1
* target/arm: Rename TBFLAG_A32, SCTLR_BRichard Henderson2021-04-301-1/+1
* Revert "target/arm: Make number of counters in PMCR follow the CPU"Peter Maydell2021-04-061-1/+0Star
* target/arm: Make number of counters in PMCR follow the CPUPeter Maydell2021-03-301-0/+1
* target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran2021-03-051-1/+14
* linux-user/aarch64: Implement PROT_MTERichard Henderson2021-02-161-0/+1
* linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLERichard Henderson2021-02-161-0/+31
* target/arm: Add support for FEAT_DIT, Data Independent TimingRebecca Cran2021-02-111-0/+12
* target/arm: Fix SCR RES1 handlingMike Nawrocki2021-02-111-0/+5
* target/arm: Implement ID_PFR2Richard Henderson2021-01-291-0/+1
* target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont2021-01-191-2/+6
* target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont2021-01-191-0/+2
* target/arm: secure stage 2 translation regimeRémi Denis-Courmont2021-01-191-1/+5
* target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont2021-01-191-0/+7
* target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont2021-01-191-14/+23
* target/arm: Define isar_feature function to test for presence of SEL2Rémi Denis-Courmont2021-01-191-0/+5
* target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont2021-01-191-2/+2
* target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont2021-01-191-0/+17
* target/arm: Add cpu properties to control pauthRichard Henderson2021-01-191-0/+10
* target/arm: Implement an IMPDEF pauth algorithmRichard Henderson2021-01-191-4/+11
* semihosting: Change common-semi API to be architecture-independentKeith Packard2021-01-181-8/+0Star
* target/arm: add aarch32 ID register fields to cpu.hLeif Lindholm2021-01-121-0/+28
* target/arm: add aarch64 ID register fields to cpu.hLeif Lindholm2021-01-121-0/+15
* target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.hLeif Lindholm2021-01-121-0/+31
* target/arm: make ARMCPU.ctr 64-bitLeif Lindholm2021-01-121-1/+1
* target/arm: make ARMCPU.clidr 64-bitLeif Lindholm2021-01-121-1/+1
* target/arm: fix typo in cpu.h ID_AA64PFR1 field nameLeif Lindholm2021-01-121-1/+1
* target/arm: ARMv8.4-TTST extensionRémi Denis-Courmont2021-01-121-0/+5
* target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell2020-12-101-0/+14
* hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell2020-12-101-0/+2
* hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell2020-12-101-0/+5
* target/arm: Implement M-profile FPSCR_nzcvqcPeter Maydell2020-12-101-0/+13
* target/arm: Refactor M-profile VMSR/VMRS handlingPeter Maydell2020-12-101-0/+3
* target/arm: Implement VSCCLRM insnPeter Maydell2020-12-101-0/+9
* arm tcg cpus: Fix Lesser GPL version numberChetan Pant2020-11-151-1/+1
* linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTIRichard Henderson2020-10-271-0/+5
* target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extensionPeter Maydell2020-10-201-0/+1
* target/arm: Implement v8.1M branch-future insns (as NOPs)Peter Maydell2020-10-201-0/+6
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