bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
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*	target/riscv: Create function to test if FP is enabled	Alistair Francis	2019-09-17	3	-10/+26
*	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	Philippe Mathieu-Daudé	2019-09-17	2	-21/+16
*	target/riscv/pmp: Restrict priviledged PMP to system-mode emulation	Philippe Mathieu-Daudé	2019-09-17	2	-5/+2
*	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen	2019-09-03	2	-6/+6
*	Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...	Peter Maydell	2019-08-22	1	-1/+1
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\| *	hw/core: Move cpu.c, cpu.h from qom/ to hw/core/	Markus Armbruster	2019-08-21	1	-1/+1
* \|	icount: remove unnecessary gen_io_end calls	Pavel Dovgalyuk	2019-08-20	1	-1/+0
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*	Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190819' into staging	Peter Maydell	2019-08-19	1	-18/+1
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\| *	target/riscv: Remove redundant declaration pragmas	Richard Henderson	2019-08-19	1	-18/+1
* \|	target/riscv: rationalise softfloat includes	Alex Bennée	2019-08-19	3	-1/+3
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*	RISC-V: Clear load reservations on context switch and SC	Joel Sing	2019-06-26	3	-1/+18
*	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt	2019-06-26	3	-0/+8
*	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt	2019-06-26	4	-0/+9
*	target/riscv: Add support for disabling/enabling Counters	Alistair Francis	2019-06-25	3	-5/+14
*	target/riscv: Remove user version information	Alistair Francis	2019-06-25	2	-25/+9
*	target/riscv: Require either I or E base extension	Alistair Francis	2019-06-25	1	-0/+6
*	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis	2019-06-25	1	-3/+5
*	target/riscv: Add the mcountinhibit CSR	Alistair Francis	2019-06-25	2	-2/+16
*	target/riscv: Add the privledge spec version 1.11.0	Alistair Francis	2019-06-24	2	-1/+2
*	target/riscv: Restructure deprecatd CPUs	Alistair Francis	2019-06-24	2	-14/+17
*	RISC-V: Fix a PMP check with the correct access size	Hesham Almatary	2019-06-24	1	-2/+1
*	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	Hesham Almatary	2019-06-24	1	-4/+5
*	RISC-V: Check PMP during Page Table Walks	Hesham Almatary	2019-06-24	2	-1/+10
*	RISC-V: Check for the effective memory privilege mode during PMP checks	Hesham Almatary	2019-06-24	3	-5/+13
*	RISC-V: Raise access fault exceptions on PMP violations	Hesham Almatary	2019-06-24	1	-3/+6
*	RISC-V: Only Check PMP if MMU translation succeeds	Hesham Almatary	2019-06-24	1	-0/+1
*	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark	2019-06-24	3	-0/+19
*	target/riscv: Fix PMP range boundary address bug	Dayeol Lee	2019-06-24	1	-1/+1
*	target/riscv: Allow setting ISA extensions via CPU props	Alistair Francis	2019-06-24	2	-2/+79
*	Supply missing header guards	Markus Armbruster	2019-06-12	3	-0/+15
*	Include qemu-common.h exactly where needed	Markus Armbruster	2019-06-12	3	-3/+0
*	qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h	Markus Armbruster	2019-06-11	1	-0/+1
*	cpu: Remove CPU_COMMON	Richard Henderson	2019-06-10	1	-3/+0
*	cpu: Introduce CPUNegativeOffsetState	Richard Henderson	2019-06-10	1	-0/+1
*	cpu: Introduce cpu_set_cpustate_pointers	Richard Henderson	2019-06-10	1	-2/+1
*	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson	2019-06-10	1	-2/+0
*	target/riscv: Use env_cpu, env_archcpu	Richard Henderson	2019-06-10	4	-21/+13
*	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson	2019-06-10	1	-1/+0
*	cpu: Define ArchCPU	Richard Henderson	2019-06-10	1	-0/+1
*	cpu: Define CPUArchState with typedef	Richard Henderson	2019-06-10	1	-2/+2
*	tcg: Split out target/arch/cpu-param.h	Richard Henderson	2019-06-10	2	-17/+27
*	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens	2019-05-24	1	-1/+3
*	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens	2019-05-24	1	-2/+5
*	target/riscv: Add checks for several RVC reserved operands	Richard Henderson	2019-05-24	2	-3/+14
*	target/riscv: Add the HGATP register masks	Alistair Francis	2019-05-24	1	-0/+11
*	target/riscv: Add the HSTATUS register masks	Alistair Francis	2019-05-24	1	-0/+18
*	target/riscv: Add Hypervisor CSR macros	Alistair Francis	2019-05-24	1	-3/+6
*	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis	2019-05-24	1	-9/+8
*	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis	2019-05-24	1	-3/+2
*	target/riscv: Improve the scause logic	Alistair Francis	2019-05-24	1	-1/+1